RTL Designer
Akuaro
- Barcelona
- Permanente
- Tiempo completo
with either a strong RTL or a strong architecture/microarchitecture background
interested in working in several areas of a RISC-V design for an advanced technology node. In
particular, areas of focus will be the processor pipeline, d-cache, i-cache, the l2-pipeline and a custom
memory controller. We believe in very “vertical” engineers that fully understand the problem to be solved
and can take it down to RTL level.
Requirements
- Bachelor's degree in computer science
- English C1
- Knowledge in Verilog
- Scripting