
Staff Engineer, Mixed Signal Design Verification
- Valencia
- Permanente
- Tiempo completo
- Acting as a mixed signal verification team member in a multi-disciplinary (Digital/Analog/DV/Implementation/Layout) multi-site development team
- Contribute towards verification strategy and methodology improvement
- Understand device requirements and come up with traceable AMS verification plan
- Code/generate SVRNM models of required analog blocks and validate against schematic.
- Develop directed tests in AMS environment or reuse constrained random UVM testcases
- File and track bugs to closure in Jira
- Document results of assigned tasks and review the results with the team
- Electronic Engineering degree with 8+ years’ experience as in chip level AMS (analog mixed signal) verification of SOC
- Familiarity with latest digital verification methodologies like digital mixed signal verification (DMS) using UVM
- Fluent with Cadence-based flow- Create schematics, Simulator/Netlist options etc.
- Experience with mixed signal simulators such as Cadence AMS or equivalent
- Experience with SVRNM or verilogams behavioural model coding for analog blocks
- Strong coding, object-oriented programming, and documentation skills.
- Experience with a scripting language (Python, C, Perl, etc.) would be an advantage
- Team player with good analysing and debugging skills
- Some limited travel should be expected.