
Principal Engineer, Design Verification
- Valencia
- Permanente
- Tiempo completo
- Verification of complex designs and sub-systems using leading edge verification methodologies
- Contribute to and Influence the decisions on methodologies/strategies to be adopted for design verification.
- Develop testbench architectures and develop using UVM or Formal based verification approaches.
- Define verification-plans, functional coverage, tests and verification methodology for block/chip-level verification. Work with the design team in generating verification-plans and closure metrics.
- Debugging of Gate Level Simulation (GLS), waiving Timing Violations approved by designer
- Continuous interaction with analog co-sim and firmware team.
- Technically mentor and guide junior verification engineers on SoC Verification.
- Support post-silicon verification activities of the products working with design, product evaluation and applications engineering team
- Lead verification efforts at IP or SoC level, effort estimation, project scheduling and tracking, task assignment, reporting to management or customer.
- Bachelor's or master’s degree, in Engineering (Electronic Engineering) or equivalent
- Building and leading small verification teams. Strong interpersonal, teamwork and communication skills are essential. Be self-motivated and enthusiastic. Strong level of English speaking and writing.
- Customer facing experience as verification lead
- Experience in both IP and SoC level verification.
- Strong demonstrable knowledge of verification-plan generation, coverage analysis, constrained random techniques, assertion based and formal verification techniques with System Verilog.
- Demonstrated experience in verification techniques for one or more of the following DSP/Processor subsystems/Formal verification
- Expert in developing unit and SoC level test benches using UVM. Integrate the block testbench in chip-level UVM environment and verify integration.
- Excellent debugging and analytical skills.
- Proficiency in scripting languages and utilities including Makefile, Python, TCL/tsh, Perl etc.
- 10-15 years in ASIC design verification.
- Experience with HW emulation or FPGA prototyping
- Low power methodologies , e.g. UPF
- Experience in behavioural modelling of analogue circuits
- Experience in verifying processor based designs
- Knowledge of interface protocols e.g. AHB/APB/AXI/I2C/SPMI