Senior Digital Design and Verification Engineer
- Valencia
- Permanente
- Tiempo completo
- Interpretation of product requirements and participation in architecture planning discussions
- Development and optimization of digital logic blocks and systems, including communication ports, digital signal processing components, clocking infrastructures, and other digital functions as needed
- Comprehensive documentation including architecture and design reviews
- Comprehensive design verification plans for digital blocks and systems
- Development of verification components including testbench agents, scoreboard code, testcases, as well as overall testbench design
- Experience developing and testing synthesized RTL designs using Verilog
- Understanding of how RTL logic designs convert to synthesized gates and the power, area, and timing tradeoffs associated with different logic design techniques
- Experience writing testbench code in Verilog for testing RTL designs
- Experience simulating and debugging both RTL designs and associated gate-level structural netlist
- Experience using synthesis and place-and-route tools
- Understanding of timing constraints and how to write and interpret them based on given timing specifications
- Expertise in UVM for verification and testbench development
- Understanding of DSP topics such as digital filter design and frequency domain signal analysis